`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/03/16 10:29:44
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module top(
        input wire clk, rst,
        output wire jump, branch, alu_a_src, memtoreg, memwrite, regwrite,
        output wire [1:0] alu_b_src,
        output wire [2:0] extop,
        output wire [3:0] alu_ctr, 
        output wire [31:0] inst,
        output wire [31:0] pc, pc_next_jump, 
        output wire [31:0] imm, reg_data_1, reg_data_2, 
        output wire [31:0] alu_srcA, alu_srcB, alu_result, 
        output wire [31:0] reg_data_write,
        output wire [31:0] mem_rdata
    );

    rv32i CPU(
              .clk(clk),
              .rst(rst),
              .mem_rdata(mem_rdata),
              .inst(inst),
              
              .jump(jump),
              .branch(branch),
              .alu_a_src(alu_a_src),
              .memtoreg(memtoreg),
              .memwrite(memwrite),
              .regwrite(regwrite),
              .alu_b_src(alu_b_src),
              .extop(extop),
              .alu_ctr(alu_ctr),
              
              .pc(pc),
              .pc_next_jump(pc_next_jump),
              .imm(imm),
              .reg_data_1(reg_data_1),
              .reg_data_2(reg_data_2),
              .alu_srcA(alu_srcA), 
              .alu_srcB(alu_srcB),
              .alu_result(alu_result),
              .reg_data_write(reg_data_write)
          );


    // inst-ram
    instr_rom instr_rom(
                  .addr     (pc[9:0]),
                  .inst     (inst)
              );

    //ram
    data_ram data_ram(
                 //ports
                 .clk       ( ~clk     		),
                 .addr    	( alu_result[9:0]),
                 .data_w  	( reg_data_2  ),
                 .mem_r_w 	( memwrite 	),
                 .data_r  	( mem_rdata )
             );
endmodule
